1. Technical Field of the Invention
This invention relates generally to wireless communications and in particular to oscillation circuits that may be used to facilitate such wireless communications.
2. Description of Related Art
Communication systems are known to support wireless and wire lined communications between wireless and/or wire lined communication devices. Such communication systems range from national and/or international cellular telephone systems to the Internet to point-to-point in-home wireless networks. Each type of communication system is constructed, and hence operates, in accordance with one or more communication standards. For instance, wireless communication systems may operate in accordance with one or more standards including, but not limited to, IEEE 802.11, Bluetooth, advanced mobile phone services (AMPS), digital AMPS, global system for mobile communications (GSM), code division multiple access (CDMA), local multi-point distribution systems (LMDS), multi-channel-multi-point distribution systems (MMDS), and/or variations thereof.
Depending on the type of wireless communication system, a wireless communication device, such as a cellular telephone, two-way radio, personal digital assistant (PDA), personal computer (PC), laptop computer, home entertainment equipment, et cetera communicates directly or indirectly with other wireless communication devices. For direct communications (also known as point-to-point communications), the participating wireless communication devices tune their receivers and transmitters to the same channel or channels (e.g., one of the plurality of radio frequency (RF) carriers of the wireless communication system) and communicate over that channel(s). For indirect wireless communications, each wireless communication device communicates directly with an associated base station (e.g., for cellular services) and/or an associated access point (e.g., for an in-home or in-building wireless network) via an assigned channel. To complete a communication connection between the wireless communication devices, the associated base stations and/or associated access points communicate with each other directly, via a system controller, via the public switch telephone network, via the Internet, and/or via some other wide area network.
For each wireless communication device to participate in wireless communications, it includes a built-in radio transceiver (i.e., receiver and transmitter) or is coupled to an associated radio transceiver (e.g., a station for in-home and/or in-building wireless communication networks, RF modem, etc.). As is known, the transmitter includes a data modulation stage, one or more intermediate frequency stages, and a power amplifier. The data modulation stage converts raw data into baseband signals in accordance with a particular wireless communication standard. The one or more intermediate frequency stages mix the baseband signals with one or more local oscillations to produce RF signals. The power amplifier amplifies the RF signals prior to transmission via an antenna.
As is also known, the receiver is coupled to the antenna and includes a low noise amplifier, one or more intermediate frequency stages, a filtering stage, and a data recovery stage. The low noise amplifier receives inbound RF signals via the antenna and amplifies then. The one or more intermediate frequency stages mix the amplified RF signals with one or more local oscillations to convert the amplified RF signal into baseband signals or intermediate frequency (IF) signals. The filtering stage filters the baseband signals or the IF signals to attenuate unwanted out of band signals to produce filtered signals. The data recovery stage recovers raw data from the filtered signals in accordance with the particular wireless communication standard.
The transceiver further includes a local oscillator generator (LO GEN) that produces the local oscillations used by the receiver section and by the transmitter section. Typically, the LO GEN will include a fractional-N synthesizer, which is capable of synthesizing frequencies over wide bandwidths with narrow channel spacing. As with most electronic devices, the demand for high performance universal frequency synthesizers is growing with the increasing performance and integration requirements of wireless communications systems such as cellular telephones and PDAs. The driving forces are lower cost, smaller form factors, and lower power consumption for consumer end products.
As is known, fractional-N phase locked loop (PLL) frequency synthesis is a popular indirect frequency synthesis method for high performance applications such as cellular telephony due to its agility and the ability of synthesizing frequencies over wide bandwidths with narrow channel spacing. For example, in GSM cellular telephony, one pair of RF bands, i.e., transmit and receive bands, consists of the frequencies 880.2 MHz to 914.8 MHz and 925.3 Mhz to 959.9 MHz, respectively. In these bands, the channel spacing is 200 kHz. In addition, the GSM standard requires synthesizer settling to an absolute accuracy of 90 Hz within approximately 280 us.
Such a fractional-N PLL frequency synthesizer may include a precise crystal oscillator providing a reference frequency, a phase and frequency detector (PFD), a charge pump (CP), a low pass loop filter (LPF), a voltage controlled oscillator (VCO), and a multiple divider blocks in the feedback path that each divide the incoming signal by some integer of either fixed or programmable value. Typically, the fixed dividers are in the front-end of the divider chain, while the programmable divider—also referred to as the multi-modulus divider (MMD)—is the last divider stage before the feedback signal is inputted to the PFD feedback terminal. Typically, the MMD is only capable of dividing by a small number of different integer divide values.
Two fixed divide-by-2 blocks allows for the synthesizer to easily generate in-phase (I) and quadrature (Q) carrier signals in four different GSM bands, namely the bands around 850 MHz, 900 Mhz, 1800 Mhz, and 1900 MHz, by tuning the VCO appropriately around 3.6 GHz. In fact, without the fixed divide-by-2 blocks, two separate VCOs would have to be employed to support this wide range of frequency tuning. The four RF bands of GSM are also referred to as the GSM850, GSM900, DCS, and PCS bands, respectively.
In a properly designed system, the feedback loop properties of the fractional-N PLL results in the VCO output “locking” to a frequency equal to the product of crystal oscillator reference frequency and the “average” divide ratio of the divider chain. A known method of generating an “average” divide ratio by selecting from a few integer divide values is to employ an over-sampling ΔΣ modulator to control the selection of divide ratios of the MMD. Internally, the MMD selects a certain integer divide ratio for the next cycle based on the integer output of the ΔΣ modulator. The selection of a new divide ratio is triggered by a rising edge of the MMD output, and hence occurs with a rate approximately equal to the reference frequency.
Briefly, an all-digital ΔΣ modulator is capable of reproducing a high resolution constant input value, for example a 20-bit value, as the average of a long sequence of coarse integer valued outputs, for example binary outputs. Specifically, on a sample-by-sample basis, the coarse ΔΣ modulator output selects the divide ratio for the next cycle. By alternating pseudo randomly between integer divide ratios, the ΔΣ modulator can effectively interpolate a fractional division ratio with fine resolution such that the frequency resolution requirements of high performance applications, such as cellular telephony, can be accommodated for.
For example, suppose it is desired that the GSM output of the fractional-N PLL frequency synthesizer lock to a frequency of 890.0 MHz, and suppose that it employs a 26 MHz crystal reference oscillator. It follows that the average divide ratio of the MMD must be equal to 890/26=34.2308 . . . . Thus, the “Channel Select” input to the ΔΣ modulator is the number 890/26 represented with high accuracy, for example 20 bits. It is the task of the ΔΣ modulator to output only integer valued samples, corresponding to the available divide values of the MMD, in such a fashion that the average value of the outputs equals 890/26. This average divide ratio can be achieved in various ways. For example, if a ΔΣ modulator with binary output is employed, the MMD divides by 33 whenever the ΔΣ modulator output equals −1, and the MMD divides by 35 whenever the ΔΣ modulator output equals 1. The ΔΣ modulator chooses between the divide ratios 33 and 35 in such a pattern that the average ratio is 890/26 and such that the sample-by-sample error—equal to the difference between the chosen integer divide value and the ratio 890/26—is modulated to predominantly occupy high frequencies. By providing this spectral shaping of the divide error, most of the error can be removed by the low pass loop filter (LPF), resulting in a high quality output oscillation, or, equivalently, an output oscillation with very little “phase noise”, approximately as if the feedback path implemented a true fractional divider.
For fractional-N PLL frequency synthesis, two types of ΔΣ modulators have been used. One is the so-called “single-quantizer” ΔΣ modulator and the other is the so-called “MASH” ΔΣ modulator. For a single-quantizer ΔΣ modulators, the output is typically a few bits, but can be as coarse as a single bit. Further, the prior art ΔΣ modulator consists of three integrators and gains g1, g2 and g3 coupled in a feedforward constellation. For the purposes of performance analysis, the ΔΣ modulator is often represented in the linearized model. In this model, the quantization noise, q[n], is modeled as a white, additive noise source, uncorrelated with the input. The quantization noise transfer function, NTF, describes the transfer function between the output y[n] and q[n], i.e., NTF(z)=Y(z)/Q(z) and is used to—both qualitatively and quantitatively—estimate the quantization noise floor at the ΔΣ modulator output. For the prior art ΔΣ modulator, it can be shown that the ΔΣ modulator yields an NTF that, for low frequencies, satisfiesNTF(z)∝(1−z−1)3.Thus, three coincident zeros at DC are present in the NTF, and hence quantization noise is rejected strongly close to DC and increases monotonically for higher frequencies.
For MASH ΔΣ modulators, the output is always multi-bit since multiple quantizer outputs are combined to form the overall MASH ΔΣ modulator output y[n]. Again, it can be shown that the NTF possesses three coincident zeros at DC.
For wide-band fractional-N PLL frequency synthesizers, the ΔΣ modulator architecture should be chosen carefully. In addition to the in-band noise shaping, the out-of-band shaped noise substantially affects the synthesizer phase noise performance. Comparing the noise shaping performance of the multi-bit single-quantizer ΔΣ modulator and the MASH ΔΣ modulator, the former can achieve more desirable noise shaping because of lower out-of-band noise power, but the latter represents a simpler, high-order ΔΣ modulator architecture with no stability problem. In addition, MASH ΔΣ modulators generate more wide-spread output patterns, and thus impose more stringent requirements on the phase detector design. Widely spread ΔΣ modulator output value patterns make the synthesizer more sensitive to substrate noise coupling since the ΔΣ modulator turn-on time of the charge pump in the locked condition is larger than a ΔΣ modulator with fewer bit of output resolution. With its susceptibility to substrate noise coupling, this phenomenon is particularly troublesome in CMOS implementations. Thus, to minimize substrate noise coupling, the output resolution of the ΔΣ modulator should ideally be single bit, since this yields the shortest turn-on time of the charge pump in locked condition.
Therefore, a need exists for a delta sigma modulator that produces a single bit output to reduce susceptibility to substrate noise coupling and improved quantized noise shaping properties.